`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   01:13:21 09/21/2012
// Design Name:   RAM
// Module Name:   /home/edgar/Escritorio/ComprobadorRAM/RAM_tb.v
// Project Name:  ComprobadorRAM
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RAM
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RAM_tb;

	// Inputs
	reg [3:0] Direccion_i;
	reg Write_Enable_i;
	reg Output_Enable_i;
	reg [7:0] Datos_Entrada_i;

	// Outputs
	wire [7:0] Datos_Salida_o;

	// Instantiate the Unit Under Test (UUT)
	RAM uut (
		.Direccion_i(Direccion_i), 
		.Write_Enable_i(Write_Enable_i), 
		.Output_Enable_i(Output_Enable_i), 
		.Datos_Entrada_i(Datos_Entrada_i), 
		.Datos_Salida_o(Datos_Salida_o)
	);

	initial begin
		// Initialize Inputs
		Direccion_i = 0;
		Write_Enable_i = 0;
		Output_Enable_i = 0;
		Datos_Entrada_i = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		// Initialize Inputs
		Direccion_i = 14;
		Datos_Entrada_i = 7;
		#20;
		Write_Enable_i = 1;
		#50;
		Write_Enable_i = 0;
		#30;
		
		Direccion_i = 2;
		Datos_Entrada_i = 10;
		#20;
		Write_Enable_i = 1;
		#50;
		Write_Enable_i = 0;
		#30;
		
		Direccion_i = 5;
		Datos_Entrada_i = 15;
		#20;
		Write_Enable_i = 1;
		#50;
		Write_Enable_i = 0;
		#30;
		
		Direccion_i = 2;
		Output_Enable_i = 1;
		#40;
		Output_Enable_i = 0;
		#30;
		
		Direccion_i = 5;
		Output_Enable_i = 1;
		#40;
		Output_Enable_i = 0;
		#30;
		
		Direccion_i = 14;
		Output_Enable_i = 1;
		#40;
		Output_Enable_i = 0;

	end
      
endmodule

